Magnetoresistive Random Access Memory (MRAM), based on the integration of silicon CMOS with MTJ technology, is a major emerging technology that is highly competitive with existing semiconductor memories such as SRAM, DRAM, and Flash. Recently, a spin transfer torque (STT) magnetization switching design described by C. Slonczewski in “Current driven excitation of magnetic multilayers”, J. Magn. Magn. Mater. V 159, L1-L7 (1996), has been extensively studied as a candidate for memory applications because of its nonvolatility, fast write time, and scalability with CMOS technology.
As shown in FIG. 1, one version of a STT-MRAM memory cell 1 has a transistor 3 connected in series with a magnetic tunnel junction (MTJ) 11. The transistor includes a gate 5 formed above a p-type semiconductor substrate 2, a source 3, and a drain 4, and is controlled by a word line (WL) 7 that is located above the gate. A bottom surface of the MTJ is connected to the drain through a bottom electrode (BE) 10, via 13, and a Cu stud 8. Source line 9 is connected through a Cu stud 6 to bit line (BL) 12 which contacts a top surface of the MTJ. During a read or write operation, a DC current flows across the MTJ from top surface to bottom surface, or vice versa, depending on the voltage applied to BL 12 and to source line (SL) 9.
Similar to MRAM, STT-RAM has a MTJ based on a tunneling magneto-resistance (TMR) effect wherein a stack of layers has a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer called a tunnel barrier layer. One ferromagnetic layer has a magnetization that is fixed in a first direction and is often referred to as a reference layer. The second ferromagnetic layer is referred to as the free layer and has a magnetization that is able to switch to a direction which is either parallel or anti-parallel to the first direction. A parallel magnetization condition is called a “0” memory state while a condition where anti-parallel magnetizations exist for the reference layer and free layer is a “1” memory state. During a read process, the “0” memory state is detected by measuring a lower resistance value across the MTJ than for a “1” memory state. A write process involves setting BL voltage to 0 and SL to a high voltage, or setting SL to 0 volts and BL at a high voltage to drive current across the MTJ. The resulting write current must be greater than the critical current needed for the free layer switching process. Moreover, the current used for the read operation is usually an order of magnitude less than that of the write operation to avoid accidently switching the free layer magnetization direction.
STT-MRAM has an advantage over conventional MRAM in avoiding the well known half select issue and writing disturbance between adjacent cells. The spin-transfer effect arises from the spin dependent electron transport properties of ferromagnetic-spacer-ferromagnetic multilayers. When a spin-polarized current transverses a magnetic multilayer in a current perpendicular-to-plane (CPP) configuration, the spin angular moment of electrons incident on a ferromagnetic layer interacts with magnetic moments of the ferromagnetic layer near the interface between the ferromagnetic and non-magnetic spacer. Through this interaction, the electrons transfer a portion of their angular momentum to the ferromagnetic layer. As a result, spin-polarized current can switch the magnetization direction of the ferromagnetic layer if the current density is sufficiently high, and if the dimensions of the multilayer are small.
For STT-MRAM to be viable in the 90 nm technology node and beyond, the ultra-small MTJs (also referred to as nanopillars or nanomagnets) must exhibit a TMR ratio that is much higher than in a conventional MRAM MTJ which uses AlOx as the tunnel barrier and a NiFe free layer. TMR ratio is (RAP−RP)/RP where RAP is the resistance of the aforementioned anti-parallel state and RP is the resistance value for the parallel state. Furthermore, critical current density (Jc) must be lower than about 106 A/cm2 to be driven by a CMOS transistor that can typically deliver 100 μA per 100 nm gate width. A critical current for spin transfer switching (Ic), which is defined as [(Ic++Ic−)/2], for a 180 nm node sub-micron MTJ having a top-down oval shaped area of about 0.2×0.4 micron, is generally a few milliamperes. Critical current density (Jc), for example (Ic/A), is on the order of several 107 A/cm2. This high current density, which is required to induce the spin-transfer effect, could destroy a thin tunnel barrier made of AlOx, MgOx, or the like. Thus, for high density devices such as STT-RAM on a gigabit scale, it is desirable to decrease Ic (and its Jc) by about an order of magnitude to avoid an electrical breakdown of the MTJ device and to be compatible with the underlying CMOS transistor that is used to provide switching current and to select a memory cell.
STT-MRAM has been plagued by intermediate states during a write process. T. Min et al. in “A Study of Write Margin of Spin Torque Transfer Magnetic Random Access Memory Technology”, IEEE Trans. on Magnetics, Vol. 46, No. 6, p. 2322-2327 (2010) describe the abnormal write behavior as “bifurcated switching” that increases programming voltage and degrades write margin. In FIG. 2, a plot of bit error rate (BER) vs. applied voltage across the MTJ shows a ballooning effect in the curve at low probabilities. In other words, there is another switching branch of the BER curve at a lower BER level (low probability bifurcated switching or LPBS) in a certain percentage of MTJs that is highly repeatable. While the number of MTJs showing the ballooning effect is small, and can be replaced by redundancy in principle, it is difficult to identify the problem bits without lengthy testing down to at least the 10−3 to 104 level. The bifurcated switching issue is considered a soft error and has become a serious source of errors during the STT-MRAM write process.
Another important feature of the bifurcated switching phenomenon is the pulse width dependence. As indicated in FIG. 3 that is taken from the T. Min reference, one observes the error rate caused by the intermediate states does not drop off significantly with longer pulses. Between pulse widths of 10 ns to 50 ns and with an assisting easy axis field (Hx)=60 Oe, error rate resulting from intermediate state formation during the write process does not change appreciably. In comparison, the nominal error rate from the spin torque transfer has decreased significantly between 10 ns and 50 ns pulse widths. For example, at 300 mV of applied voltage, the error rate drops off by about three decades by increasing pulse width to 50 ns from 10 ns. This behavior can be understood in terms of a relatively long lifetime of the intermediate states in the presence of a write current. Because of the long lifetime, longer pulses do not significantly reduce the intermediate state induced errors. The bifurcated switching behavior presents a serious challenge to achieving commercialization for 64 Mb STT-MRAM where a 10−9 bit error rate is needed in both read and write operations. Furthermore, shrinkage in the write margin between the minimum programming voltage for 10−9 BER and the dielectric breakdown of a MgO tunnel barrier layer is undesirable at a time when a larger write margin is needed for reliable 64 Mb STT-MRAMs.
Several strategies have been proposed to mitigate the intermediate state induced error in MTJs that exhibit the bifurcated switching problem. One idea is to modify the free layer composition to discourage the formation of domains. A second option is to use MRAM designs with much smaller MTJ size from a top-down perspective since energy considerations would make domain formation unfavorable as MTJ size becomes smaller than domain wall width. Current technology has not provided an acceptable solution to the aforementioned bifurcated switching issue. Therefore, the problem must be resolved by a method that is independent of MTJ size, and does not rely on material changes in MTJ layers that often improve one magnetic property but tend to degrade one or more other properties.